1. Technical Field
The present disclosure relates to a memory device, a memory system and a method of inputting/outputting data into/from the memory device.
2. Discussion of the Related Art
FIG. 1 is a, conceptual diagram illustrating a data input/output operation of a conventional synchronous dynamic random access memory (SDRAM).
Referring to FIG. 1, data are transferred from/to the conventional SDRAM 10 *once in one period of an external clock. When a frequency of the external clock for input/output of data is 100 MHz, a frequency of an array access clock to access a memory cell array inside the. SDRAM is also 100 MHz, identical to that of the external clock.
In FIG. 1, when a toggling rate for a DQ pin that indicates a data input/output (I/O) speed of a DRAM is as low as 100 Mbps, a frequency of the external clock signal may be configured to be the same as the data I/O speed.
As the data I/O speed required by the memory system becomes faster, a double data rate (DDR) memory device has been developed. This device doubles the data I/O speed in a way that data are respectively transferred at both a rising edge and a falling edge of one period of a memory internal clock. The DDR memory also adapts to a prefetch technique.
FIG. 2 is a conceptual diagram illustrating a data I/O operation of a conventional DDR memory.
When row lines are accessed, the DDR memory 20 latches data from memory cells, at sense amplifiers that are attached to each of the row lines. The prefetch technique transfers every two of the data of the memory cells of the respective row lines through multiple data paths at the same time, instead of conventionally transferring the data of one of the memory cells of the respective row lines through one data path.
For example, the DDR memory 20 may include internally a plurality of parallel data paths operating with a 100 MHz frequency access clock to access a memory cell array. At a data I/O circuit, the DDR memory outputs each data output of the plurality of parallel data paths through each DQ pin, synchronized with a 200 MHz frequency clock. As a result, the speed of data I/O is increased by two times.
Exemplary cases of including two, four and eight parallel data paths are respectively referred to as 2-bit prefetch, 4-bit prefetch and 8-bit prefetch. A burst length, which is a minimum number of data transferred at the same time for one read command or one write command, corresponds to two, four and eight for the respective prefetch cases.
FIG. 3 is a conceptual diagram illustrating a data I/O operation of a conventional Rambus dynamic random access memory (RDRAM) 30. The RDRAM 30 uses the 8-bit prefetch technique and the data I/O speed of the RDRAM is eight times greater than a frequency of the memory cell array access clock.
When eight DRAMs having ×8 I/O pins constitute one memory module, a memory controller may be connected with the memory module by a 64-bit, that is, 8 bytes, system bus.
If single data rate (SDR) memory devices are mounted on the memory module, 8 bytes of data are transferred through the system bus at one read command or one write command, because the burst length, which is a minimum unit of data transferred according to a given column address, is one. A DDR memory adapting the 2-bit prefetch technique transfers 16 bytes through the system bus at one read command or one write command, because the burst length is two: a DDR2 memory adapting the 4-bit prefetch technique transfers 32 bytes (a burst length 4) and a DDR3 memory adapting the 8-bit prefetch technique transfers 64 bytes (a burst length 8).
FIG. 4 is a table showing a range of typical data I/O speed and access speed of the memory cell array according to the conventional SDR, DDR, DDR2, DDR3 memory devices.
Referring to FIG. 4, a data I/O speed is 2n times greater than an access speed to a memory cell array of a DRAM, where n denotes a number of prefetched bits. For example, for the DDR3 memory with the 8-bit prefetch technique, the access speed to the memory cell array is ranged from about 100 to 200 MHz, and the data I/O speed is ranged from about 800 to 1600 MHz, which is eight times greater than the access speed to the memory cell array.
FIG. 5 is a block diagram illustrating a configuration of an 8-bit prefetch DDR3 memory device. FIG. 6 is a timing diagram of a data read operation of the 8-bit prefetch DDR3 memory device in FIG. 5. An external clock CLK1 is about 400 MHz, an access clock CLK21 to a memory cell array is about 100 MHz, and the data I/O data clock CLK is about 800 MHz, in the circuit shown in FIG. 5.
The 100 MHz access clock CLK21 may be generated by dividing an external clock, for example, a 400 MHz clock, by four using a frequency divider 505a. The 800 MHz data I/O clock CLK3 may be generated by multiplying the external clock CLK1 by two using a frequency multiplier 583.
Referring to FIG. 5, the 8-bit prefetch DDR3 memory includes an address buffer 501, a row latch 503, a row decoding section 510, a column latch 507, a prefetch section 550, a memory cell array 520, a bitline sense amplifier section 530, a column select section 540, an output buffer section 560 and a data pin (DQ) 581. An address path and a data output path are illustrated in FIG. 5, however, a command path and a data input path are not illustrated in FIG. 5.
The 400 MHz external clock CLK1 is applied to the row latch 503 and a row predecoder 511, and the 100 MHz access clock CLK21 is applied to the column latch 507 and a column predecoder 521. The data I/O clock CLK3 is applied to each latch 561 in the output buffer section 560.
After an address ADDR is inputted into the memory device, a row address in the address ADDR that is transferred through the address buffer 501 is latched at the row latch 503 in synchronization with the external clock CLK1 to be decoded at the row decoding section 510, which includes the row predecoder 511 and a row decoder 513. A column address in the address ADDR is latched at the column latch 507 in synchronization with the access clock CLK21, and then is decoded at a column predecoder 551 and a column decoder 553 in the prefetch section 550 in synchronization with the access clock CLK21.
When a read command READ is activated and a row line according to the row address is activated, data on memory cells connected to the activated row line are latched at the bitline sense amplifier section 530. A column line in the column select section 540 corresponding to the column address is activated and the data latched at the bitline sense amplifier section 530 are transferred through the data I/O lines.
The data from the data I/O lines are respectively amplified by I/O sense amplifiers 555, synchronized with the data I/O clock CLK3, to be latched at respective ones of the latches 561 and finally to be output via an output buffer 563 and the DQ pin 581.
Referring to FIGS. 5 and 6, the 8-bit prefetch technique shown in conjunction with the circuit of FIG. 5, transfers eight data D0 through D7 of the memory cell sharing one row line to eight data paths, synchronized with the access clock CLK21 of the memory cell array. For example, the 8-bit prefetch DDR3 memory device has eight parallel data paths to respectively access the memory cell array with the 100 MHz access clock CLK21, and to output respective output data D0 through D7 of the eight parallel data paths through the data I/O circuit and the DQ pin with the 800 MHz data I/O clock CLK3.
FIG. 7 is a block diagram illustrating a configuration of a 4-bit prefetch DDR3 memory device. FIG. 8 is a timing diagram of data read operation of the 4-bit prefetch DDR3 memory device in FIG. 7.
In FIG. 7, the 8-bit prefetch configuration of the DDR3 shown in FIG. 5 is replaced with a 4-bit prefetch configuration maintaining the same data I/O speed. For example, in FIG. 7, an access clock to a memory cell array is increased so as to be two times faster than the access clock used in FIG. 5 and the eight parallel data paths to prefetch are used instead of the four parallel data paths used in FIG. 5.
Similar to the 8-bit prefetch DDR3 memory device in FIG. 5, the external clock is about 400 MHz and the data I/O speed is about 800 MHz for a memory with the 4-bit prefetch technique. An access speed CLK22 to the memory cell array is two times greater than the access speed CLK21 of the 8-bit prefetch DDR3 memory device in FIG. 5. The 200 MHz access clock CLK22 may be generated by dividing the external clock CLK1 by two by a frequency divider 505b. 
Referring to FIGS. 7 and 8, the 4-bit prefetch technique used in the circuit of FIG. 7 delivers four data D0 through D3 from the memory cell, sharing one row line, to four data paths, in synchronization with the 200 MHz access clock CLK22. Subsequently, the next four data D4 through D7 of the memory cell, sharing the row line, are delivered to the four data paths, in synchronization with the following pulse of the 200 MHz access clock CLK22.
The 4-bit prefetch DDR memory device has four parallel data paths to access respectively the memory cell array with the 200 MHz access clock CLK22, and to prefetch the respective output data D0 through D7 in of prefetching four data at a time. The respective output data D0 through D7 of the four parallel data paths are outputted through the data I/O circuit and the DQ pin with the 800 MHz data I/O clock CLK3.
While the 8-bit prefetch DDR memory device prefetches the eight data using the 100 MHz access clock CLK21 to output the eight data at 800 Mbps through the DQ pin, the 4-bit prefetch DDR memory device prefetches the four data using the 200 MHz access clock CLK22 two times in succession to output two groups of the four data at 800 Mbps through the DQ pin.
To increase the data I/O speed of the memory device, either the access clock speed or the number of the prefetched data must be increased.
When the 4-bit prefetch configuration is used, instead of the 8-bit prefetch configuration for the same data I/O speed of the DDR3 memory device, the access clock speed may be in the range from about 200 to 400 MHz. The conventional memory core architecture, however, can hardly provide such a fast access to the memory cell array.
In the conventional memory operation, the data I/O speed is 2n times faster than the access speed to a memory cell array, as shown in FIG. 4. It is difficult to make the access speed exceed a certain level with the conventional DRAM fabrication technologies. Therefore, the minimum number of the prefetched data is increased so as to improve the speed of the data I/O, because the access clock speed is physically limited.